1. Field of the Invention
The present invention relates generally to semiconductor devices and methods of fabrication thereof and particularly to those utilizing self-aligned shallow trench isolation (SA-STI) for forming a gate electrode and an active region simultaneously.
2. Description of the Background Art
For flash memory, self-aligned shallow trench isolation (SA-STI) has conventionally been employed. SA-STI allows a floating gate electrode's polysilicon and a shallow trench isolation (STI) to be formed with a single mask in self alignment. This technique has the following advantages:
First, the STI is formed after a tunnel insulation film (or gate insulation film) is provided. This can prevent the tunnel insulation film from falling in at an end of an active region and thus thinning as typical STI would not avoid. As such, SA-STI can enhance the tunnel insulation film in reliability.
Second, a trench and a floating gate are formed with a single mask. This can prevent accumulated alignment errors and thus advantageously contribute to high integration involving microfabrication.
Furthermore, in recent years, to ensure capacitive coupling, a first polysilicon for a floating gate has a second polysilicon further deposited thereon to overhang on an STI (see SHIMIZU et al., “A Novel High-Density 5F2 NAND STI Cell Technology Suitable for 256 Mbit and 1 Gbit Flash Memories”, International Electron Devices Meeting, December 1997, pp. 271-274).
A conventional flash memory fabrication method will now be described. Initially on a semiconductor substrate a tunnel insulation film is formed and thereon a first silicon layer and a temporal passivation film implemented by a silicon nitride film are sequentially deposited. Subsequently a single mask is used to etch the silicon nitride film and the first silicon film, and the tunnel insulation film and the substrate to form a trench. Furthermore, the trench is filled with insulation film to provide a trench insulation which is in turn planarized to expose a surface of the silicon nitride film, and the silicon nitride film is then removed.
Subsequently on the first silicon layer and the trench insulation a second silicon layer is deposited for a floating gate. Then the second silicon layer on the trench insulation is partially removed to form a second silicon layer pattern to complete isolation by SA-STI.
The above described SA-STI has been improved in recent years, as disclosed as follows: in a first improvement, after the silicon nitride film is removed an oxide film is etched to recede an isolation oxide film. This can reduce residue of the first silicon layer in etching for a gate and prevent short circuit between gates. In a second improvement, a first polysilicon is used as a nucleus to selectively grow a second silicon layer. This selective growth can eliminate the necessity of patterning the second silicon layer to finely isolate adjacent gates (see Japanese Patent Laying-Open No. 2001-118944). Furthermore, in a third improvement, etching for a trench is followed by etching a first silicon layer's sidewall and a silicon substrate's sidewall to recede them. This can reduce residue of the first silicon layer in etching for a gate and prevent short circuit between gates.
Such conventional SA-STI as described above can prevent short circuit between gates, eliminate a patterning step, and the like as a silicon electrode is improved in geometry. However, the first silicon layer itself is deposited in a method selected as appropriate and at a temperature selected as appropriate, and a tunnel insulation film that contacts the first silicon layer thus deposited is impaired in characteristic. As a result, device characteristics, reliability and the like can be impaired.
For example if the first silicon layer is implemented by a polysilicon film deposited at least 600° C. to have a small thickness of at most 20 nm, it tends to be substantially all defective in withstand voltage because of a tunnel oxide film's defect. If the first silicon layer is deposited to have a thickness exceeding 70 nm, the polysilicon film will have a maximum crystal grain size larger than approximately 70 nm, however the layer may be deposited. The increased crystal grain size is promoted for example by a gate's dimensional variation and causes disadvantageously varying distribution of Vth (a value in voltage of a threshold of a transistor) after erasure operation.
As such, when the chip is seen as a whole, post-erasure Vth distribution has an increased range and recovering an overerased bit requires time, and erasure operation cannot be completed in a short period of time. Furthermore, if the recovery requires a significantly long period of time, disadvantageously reduced yield can be provided. Furthermore, for device operation, it may be necessary to introduce P or the like as dopant to reduce the first silicon layer in resistance, form a diode, and/or the like. If the first silicon layer is formed of P doped amorphous silicon, however, an increased crystal grain size is provided regardless of film thickness and a problem similar to that described above arises. To meet a demand for improved device operability, however, an appropriate concentration of P must be introduced as dopant.
As has been described above, when SA-STI is employed, controlling the quality of a polysilicon layer of a floating gate that is directly in contact with a tunnel oxide film, is significantly important in improving device performance.